1. Field of the Invention
The present invention relates to a semiconductor device comprising a gate electrode between a source electrode and a drain electrode and particularly to a semiconductor device comprising a barrier layer between a gate electrode and a channel layer.
2. Description of the Related Art
Demands for small-size and low-power consumption portable communication terminals have grown in the field of mobile communications systems. In order to implement such terminals, a power amplifier, for example, is required to be operable with a single positive voltage supply, at low voltage and with high power-added efficiency. In addition, low distortion characteristics are required for the power amplifier, especially in the advanced wireless communication system such as CDMA (Code Division Multiple Access).
Devices that have been practically utilized for such power amplifiers include a junction field effect transistor (JFET), a metal-semiconductor field effect transistor (MESFET) and a heterojunction field effect transistor (HFET).
Current modulation takes place through the use of a p-n junction in the JFET. FIG. 1 shows an example of configuration of the JFET. The JFET comprises a channel region 414 made of n-type GaAs on a substrate 11 made of semi-insulating single-crystal GaAs. The channel region 414 may be formed either directly on the substrate 11 or on a p-type layer 441 made of p-type GaAs formed on the substrate 11. A p-type region 442 made of p-type GaAs is formed on the channel region 414. A gate electrode 20 is formed in contact with the p-type region 442. The JFET further includes a depletion layer 443 at the interface between the p-type region 442 and the channel region 414. Upon an application of voltage to the gate electrode 20, the current flowing between a source electrode 18 and a drain electrode 19 (the channel region 414) is modulated.
The MESFET modulates current through the use of a Schottky junction. FIG. 2 shows an example of configuration of the MESFET. The MESFET has a configuration similar to that of the JFET shown in FIG. 1 except that the p-type region 442 is eliminated and the gate electrode 20 is formed on a channel region 514 with a depletion layer 543 in between. Upon an application of voltage to the gate electrode 20, the current flowing between the source electrode 18 and the drain electrode 19 (the channel region 514) is modulated. As shown in FIG. 2, a MESFET generally has a recessed structure wherein the thickness of the channel layer 514 near the gate electrode 20 is thin.
The HFET modulates current through the use of a hetero junction. FIG. 3 shows an example of configuration of the HFET. The HFET comprises a second barrier layer 13 of AlGaAs, the channel layer 14 of InGaAs and a first barrier layer 615 of AlGaAs stacked in this order on the substrate 11 of semi-insulating single-crystal GaAs with a buffer layer 12 of GaAs between the substrate 11 and the second barrier layer 13. The gate electrode 20 is formed on the first barrier layer 615. The barrier layers 13 and 615 each have carrier supply regions 13a and 15a including n-type impurity in high resistivity regions 13b and 15b, respectively. Upon an application of voltage to the gate electrode 20, the current flowing between the source electrode 18 and the drain electrode 19 (the channel region 14) is modulated. As shown in FIG. 3, the HFET generally has a recessed structure wherein the thickness of the barrier layer 615 near the gate electrode 20 is thin. A carrier deficient region 14a (the dotted region in FIG. 3) is formed in the channel layer 14 directly beneath the recessed region, that is, the thin part of the first barrier layer 615. The carrier deficient region 14a is a region that is depleted of carriers or has fewer carriers than the other region in the channel layer.
Although these FETs described so far each have advantages, they have disadvantages, too. For example, the JFET has an advantage in that the built-in voltage is 1.4 V that is high enough to allow an application of positive voltage of 1 V or above since the JFET uses a p-n junction gate. Another advantage is that the JFET is free from a problem of increase in xe2x80x98parasitic source resistancexe2x80x99 (resistance between the source electrode 18 and the gate electrode 20) in contrast to the conventional MESFET and the HFET. Therefore, the JFET is easily operated with a single positive voltage supply that applies positive voltage to both between the source electrode 18 and the drain electrode 19 and between the source electrode 18 and the gate electrode 20.
However the JFET has a disadvantage in that capacitance Cgs between the gate electrode 20 and the source electrode 18 (gate-source capacitance) and mutual conductance Gm significantly vary depending on gate voltage Vg since the depletion layer 443 expands or contracts upon an application of voltage to the gate electrode 20. That is, linearity of gate-source capacitance Cgs and mutual conductance Gm with respect to gate voltage Vg is not satisfactory. Distortion characteristic of the power amplifier is thereby restricted.
As in the JFET, the depletion layer 543 of the MESFET expands or contracts upon an application of positive or negative voltage to the gate electrode 20. Consequently, linearity of gate-source capacitance Cgs and mutual conductance Gm with respect to gate voltage Vg is not satisfactory. In contrast to the JFET, the built-in voltage of the MESFET is about 0.7 V, that is too low to allow an application of positive voltage of 1 V or above to the gate electrode 20. Furthermore, in the MESFET whose threshold voltage Vth is near 0 volt or positive, a part of the recessed region, that is, the thin part of the channel layer 514, over which the gate electrode 20 is not placed (the dotted region in FIG. 2) is likely to remain as a high resistivity region upon an application of positive voltage to the gate electrode 20. Source resistance is thereby raised. Consequently, on-resistance Ron is raised and it is difficult to increase maximum drain current Idmax. Power-added efficiency is thus restricted, and, it is difficult to operate the MESFET with a single positive voltage supply.
In contrast to the JFET and the MESFET, linearity of gate-source capacitance Cgs and mutual conductance Gm of HFET with respect to gate voltage Vg is excellent, because carriers are accumulated in the channel layer 14 of the HFET upon an application of positive voltage to the gate electrode 20.
However, as in the MESFET, upon an application of positive voltage of the order of 1.0 V to the gate electrode 20, carriers remain scarce in the carrier deficient region directly beneath the recessed region over which the gate electrode 20 is not placed (the dotted region in FIG. 4). Resistance Rrec in this region remains as a parasitic resistance component. As in the MESFET, power-added efficiency is thereby restricted and it is difficult to operate the HFET with a single positive voltage supply.
As thus described, no FET of related art has both characteristics. That is, no FET is easily operable with a single positive voltage supply while exhibiting excellent linearity of gate-source capacitance Cgs and mutual conductance Gm with respect to gate voltage Vg.
It is an object of the invention to provide a semiconductor device easily operable with a single positive voltage supply while exhibiting excellent linearity of gate-source capcitance Cgs and mutual conductance Gm with respect to gate voltage Vg.
A semiconductor device of the invention includes a source electrode and a drain electrode between which a gate electrode is provided. The semiconductor device comprises: a channel layer made of a semiconductor as a current path between the source electrode and the drain electrode; and a first barrier layer formed between the channel layer and the gate electrode and made of a semiconductor whose electron affinity is smaller than that of the semiconductor forming the channel layer. The first barrier layer includes a p-type low resistivity region with a high concentration of p-type impurity provided in correspondence with the gate electrode and a high resistivity region with a low concentration of impurity.
According to the semiconductor device, upon an application of voltage to the gate electrode, a carrier deficient region formed in the channel layer in correspondence with the p-type low resistivity region in the barrier layer is expanded or reduced. Since the p-type low resistivity region is provided in the barrier layer, no parasitic resistance component remains in the channel layer when a positive voltage is applied to the gate electrode. In addition, a high built-in voltage is obtained and an application of high positive voltage to the gate electrode is achieved.
Other and further objects, features and advantages of the invention will appear more fully from the following description.